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PRELIMINARY
WMS7130/1
NONVOLATILE DIGITAL POTENTIOMETERS WITH UP/DOWN (3-WIRE) INTERFACE, 10KOHM, 50KOHM, 100KOHM RESISTANCE 32 TAPS WITH OPTIONAL OUTPUT BUFFER
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Publication Release Date: April 21, 2005 Revision 1.0
WMS7130/1
1. GENERAL DESCRIPTION
The WMS713x is a 32 non-volatile linear digital potentiometers available in 10K, 50K and 100K resistance values. The WMS7130/1 can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications. The output of each potentiometer is determined by the wiper position, which varies in linearly between VA and VB terminal according to the content stored in the volatile Tap Register (TR) which is programmed through Up/Down (Increment/Decrement) interface. The channel has one non-volatile memory location (NVMEM0) that can be directly written to by users through the Up/Down interface. Power-on recall is also built in so the content of the NVMEM0 to Tap Register is automatically loaded.
B
The WMS7130/1 devices pin out the resistor wiper directly. The WMS7131 devices feature an output buffer with 3mA minimum drive capability. All the WMS7130/1 devices are single channel devices offered in 8-pin PDIP, SOIC and MSOP packages. The WMS7130/1 devices operate over a wide operating voltage ranging from 2.7V to 5.5V.
2. FEATURES
* * * * * * * * * * * * * Drop-in replacements for many popular parts Available output buffer for WMS7131 devices Single linear-taper channel 32 taps 10K, 50K and 100K end-to end resistance VSS to VDD terminal voltages Non-volatile storage of wiper positions with power-on recall Data storage and potentiometer control through Up/Down (3-wire) interface Endurance 100,000 write cycles Data retention 100 years Package options: o 8-pin PDIP, SOIC or MSOP Industrial temperature range: -40 ~ 85C Single supply operation 2.7V to 5.5V
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WMS7130/1
3. BLOCK DIAGRAM
Tap Register
VA
INC CS U/D
Decoder
Up/Down Serial Interface
VW
VB
NV Memory
VSS
NV Memory Control
NVMEM0
VDD
FIGURE 1 - WMS7130 BLOCK DIAGRAM (Rheostat Mode)
Tap Register
VA
INC CS U/D
Up/Down Serial Interface
Decoder
VW
VB
NV Memory
VSS
NV Memory Control
NVMEM0
VDD
FIGURE 2 - WMS7131 BLOCK DIAGRAM (Divider Mode)
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Publication Release Date: April 21, 2005 Revision 1.1
WMS7130/1
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 5 6. PIN DESCRIPTION ............................................................................................................................. 6 7. FUNCTIONAL DESCRIPTION............................................................................................................ 7 7.1. Potentiometer and Rheostat Modes ............................................................................................. 7 7.1.1. Rheostat Configuration .......................................................................................................... 7 7.1.2. Potentiometer Configuration .................................................................................................. 7 7.2. Non-Volatile Memory (NVMEM) ................................................................................................... 7 7.3. Serial Data Interface ..................................................................................................................... 8 7.4. Operation Overview ...................................................................................................................... 8 8. TIMING DIAGRAMS............................................................................................................................ 9 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 11 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 12 10.1 Test Circuits ............................................................................................................................... 14 11. TYPICAL APPLICATION CIRCUITS .............................................................................................. 15 11.1. Layout Considerations .............................................................................................................. 17 12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 18 13. ORDERING INFORMATION........................................................................................................... 21 14. VERSION HISTORY ....................................................................................................................... 22
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WMS7130/1
5. PIN CONFIGURATION
INC U/D VA VSS
1 2 3 4
8 7 6 5
VDD CS VB VW
INC
1
8
VDD CS
U/D
2
7
VA VSS
3
6
VB
8-MSOP
4
5
VW
8-SOIC
INC
1
8
VDD
U/D
2
7
CS
VA
3
6
VB
VSS
4
5
VW
8-PDIP
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Publication Release Date: April 21, 2005 Revision 1.1
WMS7130/1
6. PIN DESCRIPTION
TABLE 1 - PIN DESCRIPTION
Pin Name
I/O
Description Increment Control. A High-Low transition of INC when
INC
I
CS is low will move the wiper up or down for one
increment based on the U/ D input Up/Down control Input. High state will cause the wiper to move to the VB terminal, Low state to the VA terminal
B
U/ D VA VSS VDD
I I -
High terminal of WinPot Ground pin, logic ground reference Power Supply Chip Select. When CS is HIGH, the part is deselected
CS
VB
B
and the device will be in the standby mode. CS LOW enables the part, placing it in the active power mode Low terminal of WinPot Wiper terminal of WinPot (can be buffered), its position on the resistor array is controlled by the inputs on INC , U/ D , and CS
VW
O
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WMS7130/1
7. FUNCTIONAL DESCRIPTION
The WMS7130/1, a nonvolatile digitally programmable potentiometers with 32 taps, with or without output buffer, is designed to operate as both a potentiometer or a variable resistor depending upon the output configuration selected. The chip can store up to one 8-bit word in a nonvolatile memory (NVMEM0) in order to set the tap register value when the device is powered up. The WMS7130/1 is controlled by a serial Up-Down (3-wire) interface that allows setting the tap register value as well as storing data in the nonvolatile memory.
7.1. POTENTIOMETER AND RHEOSTAT MODES The WMS7130/1 can operate as either a rheostat or as a potentiometer (voltage divider). When in the potentiometer configuration there are two possible modes. One is done using WMS7130 Winpot device without the output buffer and the other mode is done with WMS7131 WinPot device with the output buffer. 7.1.1. Rheostat Configuration The WMS7130/1 acts as a two terminal resistive element in the rheostat configuration where one terminal can be connected to either the end point pins of the resistor (VA and VB) and the other terminal is the wiper (VW) pin. This configuration controls the resistance between the two terminals and the resistance can be adjusted by sending the corresponding tap register setting to the WMS7130/1 or can also be set by loading a pre-set tap register value from nonvolatile memory NVMEM0 upon power up.
B
7.1.2. Potentiometer Configuration In potentiometer configuration an input voltage is applied to either one of the end point pins (VA or VB). The voltage on the wiper pin will be proportional to the voltage difference between VA and VB and the wiper setting. The resistance cannot be directly measured in this configuration.
B B
7.2. NON-VOLATILE MEMORY (NVMEM) The WMS7130/1 has one NVMEM position available for storing the potentiometer setting. The NVMEM position can be directly written via the Up/Down interface. The potentiometer is loaded with the value stored in the NVMEM0 on power up.
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Publication Release Date: April 21, 2005 Revision 1.1
WMS7130/1
7.3. SERIAL DATA INTERFACE The Up/Down family has a 3-wire Serial Data Interface consisting of CS , INC , U/ D pins. Only UP/DOWN operations can be performed. The key features of this interface include: * * * * Increment/Decrement operations on the tap register (TR) Direct refresh of tap register (TR) from internal NVMEM Nonvolatile storage of the present tap register value into the NVMEM and automatic recall at power up For WMS7131 devices, output buffer amplifier
7.4. OPERATION OVERVIEW The wiper position or the Tap Register(TR) setting can only be changed by the UP/DOWN operation with the combination of CS , U/ D , and INC signals. When CS is low, the part will be activated and the TR setting can be changed by toggling INC , and TR will move up when U/ D is High and move down when U/ D is Low. The TR setting will be stored into the user NVMEM automatically each time
CS goes high while INC holds high. Otherwise, if INC is low when CS goes high, the TR setting
will not be stored. The NVMEM content will be automatically loaded into TR at Power On. The user NVMEM can be tested through the voltage measurement on the wiper pin after saving TR setting into the NVMEM and reloading into the TR. When the TR setting is already at LOW, further DOWN operations won't change the setting. Similarly, when TR setting is at HIGH, further UP operations won't change the setting. When CS is held HIGH, the part will be in Standby mode and the TR setting will not be changed. The operating modes of Up/Down are summarized below.
CS
Low Low Low to High Low to High High
U/ D High Low x x x
INC
Operation Wiper toward VA Wiper toward VB
B
High to Low High to Low High Low x
Store Wiper Position No Store, Return to Standby Standby
Note: x means don't care
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WMS7130/1
8. TIMING DIAGRAMS
Conditions: VDD = +2.7V to 5.5V, VA = VDD, VB = 0V, T = 25C
B
CS tCYC tIL tIH
tCI INC
tIC
(store)
tCPH
90% 90%
tF tDI U/D tID
10%
tR
tIW
MI
[1]
VW
FIGURE 3 -WMS7130/1 TIMING DIAGRAM
Note: [1] MI in the AC Timing diagram (Figure 3) refers to the minimum incremental change in the wiper output due to a change in the wiper position.
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Publication Release Date: April 21, 2005 Revision 1.1
WMS7130/1
TABLE 10 - TIMING PARAMETERS
PARAMETERS
SYMBOL tCI tDI tID tIL tIH tIC tCPH tCPH tIW tCYC tR, tF tPU
MIN. 100 50 100 250 250 1 100 15 (2.7V)
MAX.
UNITS ns ns ns ns ns s ns ms
CS to INC Setup
U/ D to INC Setup U/ D to INC Hold
INC LOW Period INC HIGH Period INC Inactive to CS Inactive CS Deselect Time (NO STORE) CS Deselect Time (STORE) INC to VW Change INC Cycle Time INC Input Rise and Fall Time
Power-Up to Wiper Stable VCC Power-Up rate
5 1 500 1 0.2 50 (54s 0-2.7V) (13ms 0-2.7V)
s s s ms V/ms
tR VCC
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WMS7130/1
9. ABSOLUTE MAXIMUM RATINGS
TABLE 11 - ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)[1] Conditions Junction temperature Storage temperature Voltage applied to any pad VDD - VSS 150C -65 to +150C (Vss - 0.3V) to (VDD + 0.3V) -0.3 to 7.0V Values
TABLE 12 - OPERATING CONDITIONS (PACKAGED PARTS) Conditions Commercial operating temperature range Extended operating temperature Industrial operating temperature Supply voltage (VDD) Ground voltage (VSS) Values 0C to +70C -20C to +70C -40C to +85C +2.7V to +5.5V 0V
[ 1]
Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions Publication Release Date: April 21, 2005 Revision 1.1
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WMS7130/1
10. ELECTRICAL CHARACTERISTICS
TABLE 12 - ELECTRICAL CHARACTERISTICS (Packaged parts) PARAMETERS Rheostat Mode Nominal Resistance Different Non Linearity Integral Non Linearity Tempo
1 [2] [2] [2]
SYMBOL R DNL INL RAB/T RW IW N
[2]
MIN. -20 -1 -1
TYP.
MAX. +20 +1 +1
UNITS % LSB LSB ppm/C
CONDITIONDS T=25C, VW open
300 50 80 -1 8 -1 -1 -1 0 VSS 30 30 0.4 0.4 +20 0 1 VDD +1 +1 1
Wiper Resistance Wiper Current Divider Mode Resolution
VDD=5V, I=VDD/RTotal VDD=2.7V, I=VDD/RTotal
mA Bits LSB LSB ppm/C LSB LSB V pF pF MHz KHz KHz VDD=5V, VB=VSS
B
Different Non Linearity Integral Non Linearity Full Scale Error Zero Scale Error Resistor Terminal
DNL INL Vw/T VFSE VZSE VA,VB,VW
B
[2] [1]
Temperature Coefficient
Code = 80h Code = Full Scale Code = Zero Scale
Voltage Range Terminal Capacitance [1] Wiper Capacitance
[1] [1]
CA, CB
B
Dynamic Characteristics Bandwidth -3dB Settling Time to 1 LSB
BW10K BW50K BW100K TS IOUT Rout THD 3 Analog Output (Buffer enables) Amp Output Current Amp Output Resistance Total Harmonic Distortion [1] Digital Inputs/Outputs Input High Voltage Input Low Voltage VIH VIL 0.7VDD
1.5 300 200 80 100
Code = 80h
uS mA VO=1/2 scale IL = 100uA VA=2.5V, VDD=5V, f=1kHz, VIN=1VRMS
1
10 0.08
%
V 0.3VDD - 12 V
WMS7130/1
PARAMETERS Output Low Voltage Input Leakage Current Output Leakage Current Input Capacitance
[1]
SYMBOL VOL ILI ILo CIN COUT VDD IDDR IDDW ISA [3]
MIN. -1 -1
TYP.
MAX. 0.4 +1 +1
UNITS V uA uA pF pF
CONDITIONDS IOL=2mA
CS =VDD,Vin=Vss ~ VDD CS =VDD,Vin=VSS ~ VDD
VDD=5V, fc = 1Mhz VDD=5V, fc = 1Mhz
25 25 2.7 0.5 1 0.5 0.1 5.5 1 2 1 1 1
Output Capacitance [1] Power Requirements Operating Voltage Operating Current Operating Current
V mA mA mA uA LSB/V All ops except NVMEM program During Non-volatile memory program Buffer is active, NOP, no load Buffer is inactive, Power Down, No load VDD=5V10%, Code=80H
Standby Current ISB [4] Power Supply Rejection Ratio PSRR
Notes: [1] Not subject to production test. [2] LSB = (VA - VB) / (T- 1); DNL = (Vi+1 - Vi) / LSB; where i = [0, (T -1)] and T = # of taps of the device.
B
INL = (Vi - i*LSB) / LSB;
[3] WMS71x1 only. [4] WMS71x0 only.
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Publication Release Date: April 21, 2005 Revision 1.1
WMS7130/1
10.1 TEST CIRCUITS
VA V+
B
VW
V+ = VDD 1LSB= V+/256 V+ VMS*
VA VW
B
V+ = VDD 10% PSRR(dB) = 20LOG( VMS ) VDD PSS(%/%) = VMS VDD
VB WMS71xx
*Assume infinite input impedance
VB WMS71xx
VMS*
*Assume infinite input impedance
Potentiometer divider nonlinearity error test circuit (INL, DNL) No Connection WMS71xx VA VW VB
B
Power supply sensitivity test circuit (PSS, PSRR)
VA IW W
WMS71xx VW
VB
B
+5V VOUT
VMS *
~
VIN
*Assume infinite input impedance
2.5V DC Offset Capacitance test circuit
Resistor position nonlinearity error test circuit (Rheostat Operation: R-INL, R-DNL) VMS * VA VW VB
B
IW = V /RTotal DD IW
WMS71xx +5V VA VIN OFFSET GND 2.5V DC
~
VW VOUT VB
B
WMS71xx
RW = V /IW MS
*Assume infinite input impedance
Wiper resistance test circuit
Gain vs. frequency test circuit FIGURE 4 - TEST CIRCUITS
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WMS7130/1
11. TYPICAL APPLICATION CIRCUITS
RA RB
Vin WMS71XX
_ OP AMP +
VOUT
VOUT = - VIN RA =
RB RA
RB =
B
RAB(256 - D) , 256
RAB D 256
RAB = Total resistance of potentiometer D = Wiper setting for WMS71XX
FIGURE 5 - PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7130/1
VIN
+
OP _ AMP
VOUT
RA
RB
B
WMS71XX VOUT = VIN (1+ RA =
RB ) RA
B
RAB(256 - D) RAB D , RB = 256 256
RAB = Total resistance of potentiometer D = Wiper setting for WMS71XX FIGURE 6 - PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7130/1 Publication Release Date: April 21, 2005 Revision 1.1
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WMS7130/1
V+
I = 32mA VREFH VREF = 5.0v WMS71xx
GND FIGURE 7 - WMS7130/1 TRIMMING VOLTAGE REFERENCE
VDD
L1 CHOKE C1 0.1uF CS\ INC\ U/D\ CS\ U/D\ INC\ VSS VDD VA VW VB RF OUT Q1 FILTER RF POWER AMP WMS71xx WINPOT C2
RF Input
FIGURE 8 - WMS7130/1 RF AMP CONTROL
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WMS7130/1
11.1. LAYOUT CONSIDERATIONS Use a 0.1F bypass capacitor as close as possible to the VDD pin. This is recommended for best performance. Often this can be done by placing the surface mount capacitor on the bottom side of the PC board, directly between the VDD and VSS pins. Care should be taken to separate the analog and digital traces. Sensitive traces should not run under the device or close to the bypass capacitors. A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals.
DIGITAL CONTROL LINES ANALOG SIGNAL LINE
INC U/D
CAP
VDD CS VB VW
DIGITAL CONTROL LINE ANALOG SIGNAL LINES
VA VSS
FIGURE 9 - WMS7130/1 LAYOUT
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Publication Release Date: April 21, 2005 Revision 1.1
WMS7130/1
12. PACKAGE DRAWINGS AND DIMENSIONS
8
5
c
E
HE
L
1
D
4
0.25 O
A Y SEATING PLANE b e A1 GAUGE PLANE
Control demensions are in milmeters .
SYMBOL A A1 b c E D e HE Y L DIMENSION IN MM MAX. MIN. 1.35 1.75 0.10 0.25 0.51 0.33 0.19 0.25 3.80 4.00 4.80 5.00 1.27 BSC 6.20 5.80 0.10 0.40 1.27 0 10 DIMENSION IN INCH MIN. MAX. 0.053 0.069 0.010 0.004 0.013 0.020 0.008 0.010 0.150 0.157 0.188 0.196 0.050 BSC 0.228 0.016 0 0.244 0.004 0.050 10
FIGURE 10: 8L 150MIL SOIC
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WMS7130/1
D
8 5
E1
1
4
B B
1
S
E c
A A2 L e1
A1
B a s e P la n e
S e a tin g P la n e
eA
S ym b o l
D im e n s io n in in c h
D im e n s io n in m m
M in
0 .0 1 0 0 .1 2 5 0 .0 1 6 0 .0 5 8 0 .0 0 8
Nom
M ax
0 .1 7 5
M in
0 .2 5
Nom
M ax
4 .4 5
A A1 A2 B B1 c D E E1 e1 L
0 .1 3 0 0 .0 1 8 0 .0 6 0 0 .0 1 0 0 .3 6 0
0 .1 3 5 0 .0 2 2 0 .0 6 4 0 .0 1 4 0 .3 8 0 0 .3 1 0 0 .2 5 5 0 .1 1 0 0 .1 4 0 15 0 .3 7 5 0 .0 4 5
3 .1 8 0 .4 1 1 .4 7 0 .2 0
3 .3 0 0 .4 6 1 .5 2 0 .2 5 9 .1 4
3 .4 3 0 .5 6 1 .6 3 0 .3 6 9 .6 5 7 .8 7 6 .4 8 2 .7 9 3 .5 6 15 9 .5 3 1 .1 4
0 .2 9 0 0 .2 4 5 0 .0 9 0 0 .1 2 0 0 0 .3 3 5
0 .3 0 0 0 .2 5 0 0 .1 0 0 0 .1 3 0 0 .3 5 5
7 .3 7 6 .2 2 2 .2 9 3 .0 5 0 8 .5 1
7 .6 2 6 .3 5 2 .5 4 3 .3 0
e S
A
9 .0 2
FIGURE 11: 8L 300MIL PDIP
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Publication Release Date: April 21, 2005 Revision 1.1
WMS7130/1
FIGURE 12: 8L 3MM MSOP
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WMS7130/1
13. ORDERING INFORMATION
Winbond's WinPot Part Number Description:
WMS71 T
B
RRR P
Winbond WinPot Products w/ Up-Down Interface
Number Of Taps: 3 = 32 For Up/Down interface: 0 : No buffer 1 : With buffer End-to-end Resistance: 010: 10Kohm 050: 50Kohm 100: 100Kohm Package: S: SOIC P: PDIP M: MSOP
Output Buffer NO
End-to-End Resistance 10K 50K 100K
SOIC WMS7130010S WMS7130050S WMS7130100S WMS7131010S WMS7131050S WMS7131100S
PDIP WMS7130010P WMS7130050P WMS7130100P WMS7131010P WMS7131050P WMS7131100P
MSOP WMS7130010M WMS7130050M WMS7130100M WMS7131010M WMS7131050M WMS7131100M
YES
10K 50K 100K
For the latest product information, access Winbond's worldwide website at http://www.winbond-usa.com
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Publication Release Date: April 21, 2005 Revision 1.1
WMS7130/1
14. VERSION HISTORY
VERSION 1.0 1.1 DATE June 2003 April 2005 Initial issue Revise disclaim section DESCRIPTION
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WMS7130/1
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. The contents of this document are provided "AS IS", and Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. In no event, shall Winbond be liable for any damages whatsoever (including, without limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if Winbond has been advised of the possibility of such damages. Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Winbond makes no representation or warranty that such applications shall be suitable for the use specified. The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond. This product incorporates SuperFlash(R). This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD(R) ChipCorder(R) product specifications. In the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is subject to change without notice. Copyright(c) 2005, Winbond Electronics Corporation. All rights reserved. ChipCorder(R) and ISD(R) are trademarks of Winbond Electronics Corporation. SuperFlash(R) is the trademark of Silicon Storage Technology, Inc. All other trademarks are properties of their respective owners.
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Publication Release Date: April 21, 2005 Revision 1.1

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